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BRCM63XX 的路由有福了 支持内置MODEM了
源码网址
https://dev.openwrt.org/browser/ ... ort.patch?rev=36957
source:trunk/target/linux/brcm63xx/patches-3.9/424-bcm3368_support.patch@36957
View diff against:
查看修订版:
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Last change on this file since 36957 was 36874, checked in by florian, 5个月 ago
brcm63xx: add support for BCM3368
Add support for the Broadcom BCM3368 cable modem chipset, includes:
Ethernet
SPI
UARTs
GPIOs
PCI
Signed-off-by: Florian Fainelli <florian@…>
File size: 16.0 KB
表式标准arch/mips/bcm63xx/Kconfig
a b config BCM63XX_EHCI
13 13 select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD
14 14 select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD
15 15
16 config BCM63XX_CPU_3368
17 bool "support 3368 CPU"
18 select HW_HAS_PCI
19
16 20 config BCM63XX_CPU_6328
17 21 bool "support 6328 CPU"
18 22 select HW_HAS_PCI
表式标准arch/mips/bcm63xx/cpu.c
a b static u8 bcm63xx_cpu_rev;
29 29 static unsigned int bcm63xx_cpu_freq;
30 30 static unsigned int bcm63xx_memory_size;
31 31
32 static const unsigned long bcm3368_regs_base[] = {
33 __GEN_CPU_REGS_TABLE(3368)
34 };
35
36 static const int bcm3368_irqs[] = {
37 __GEN_CPU_IRQ_TABLE(3368)
38 };
39
32 40 static const unsigned long bcm6328_regs_base[] = {
33 41 __GEN_CPU_REGS_TABLE(6328)
34 42 };
… … unsigned int bcm63xx_get_memory_size(voi
116 124 static unsigned int detect_cpu_clock(void)
117 125 {
118 126 switch (bcm63xx_get_cpu_id()) {
127 case BCM3368_CPU_ID:
128 return 300000000;
129
119 130 case BCM6328_CPU_ID:
120 131 {
121 132 unsigned int tmp, mips_pll_fcvo;
… … static unsigned int detect_memory_size(v
266 277 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
267 278 }
268 279
269 if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
280 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
270 281 val = bcm_memc_readl(MEMC_CFG_REG);
271 282 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
272 283 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
… … void __init bcm63xx_cpu_init(void)
302 313 chipid_reg = BCM_6345_PERF_BASE;
303 314 break;
304 315 case CPU_BMIPS4350:
305 if ((read_c0_prid() & 0xf0) == 0x10)
316 switch ((read_c0_prid() & 0xff)) {
317 case 0x04:
318 chipid_reg = BCM_3368_PERF_BASE;
319 break;
320 case 0x10:
306 321 chipid_reg = BCM_6345_PERF_BASE;
307 else
322 break;
323 default:
308 324 chipid_reg = BCM_6368_PERF_BASE;
325 break;
326 }
309 327 break;
310 328 }
311 329
… … void __init bcm63xx_cpu_init(void)
322 340 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
323 341
324 342 switch (bcm63xx_cpu_id) {
343 case BCM3368_CPU_ID:
344 bcm63xx_regs_base = bcm3368_regs_base;
345 bcm63xx_irqs = bcm3368_irqs;
346 break;
325 347 case BCM6328_CPU_ID:
326 348 bcm63xx_regs_base = bcm6328_regs_base;
327 349 bcm63xx_irqs = bcm6328_irqs;
表式标准arch/mips/bcm63xx/dev-uart.c
a b int __init bcm63xx_uart_register(unsigne
54 54 if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
55 55 return -ENODEV;
56 56
57 if (id == 1 && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
58 !BCMCPU_IS_6368())
57 if (id == 1 && !BCMCPU_IS_3368() && !BCMCPU_IS_6328() &&
58 !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
59 59 return -ENODEV;
60 60
61 61 if (id == 0) {
表式标准arch/mips/bcm63xx/prom.c
a b void __init prom_init(void)
30 30 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
31 31
32 32 /* disable all hardware blocks clock for now */
33 if (BCMCPU_IS_6328())
33 if (BCMCPU_IS_3368())
34 mask = CKCTL_3368_ALL_SAFE_EN;
35 else if (BCMCPU_IS_6328())
34 36 mask = CKCTL_6328_ALL_SAFE_EN;
35 37 else if (BCMCPU_IS_6338())
36 38 mask = CKCTL_6338_ALL_SAFE_EN;
表式标准arch/mips/bcm63xx/setup.c
a b void bcm63xx_machine_reboot(void)
68 68
69 69 /* mask and clear all external irq */
70 70 switch (bcm63xx_get_cpu_id()) {
71 case BCM3368_CPU_ID:
72 perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;
73 break;
71 74 case BCM6328_CPU_ID:
72 75 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
73 76 break;
表式标准arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
a b
9 9 * compile time if only one CPU support is enabled (idea stolen from
10 10 * arm mach-types)
11 11 */
12 #define BCM3368_CPU_ID 0x3368
12 13 #define BCM6328_CPU_ID 0x6328
13 14 #define BCM6338_CPU_ID 0x6338
14 15 #define BCM6345_CPU_ID 0x6345
… … u16 __bcm63xx_get_cpu_id(void);
22 23 u8 bcm63xx_get_cpu_rev(void);
23 24 unsigned int bcm63xx_get_cpu_freq(void);
24 25
26 #ifdef CONFIG_BCM63XX_CPU_3368
27 # ifdef bcm63xx_get_cpu_id
28 # undef bcm63xx_get_cpu_id
29 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
30 # define BCMCPU_RUNTIME_DETECT
31 # else
32 # define bcm63xx_get_cpu_id() BCM3368_CPU_ID
33 # endif
34 # define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
35 #else
36 # define BCMCPU_IS_3368() (0)
37 #endif
38
25 39 #ifdef CONFIG_BCM63XX_CPU_6328
26 40 # ifdef bcm63xx_get_cpu_id
27 41 # undef bcm63xx_get_cpu_id
… … enum bcm63xx_regs_set {
196 210 #define RSET_RNG_SIZE 20
197 211
198 212 /*
213 * 3368 register sets base address
214 */
215 #define BCM_3368_DSL_LMEM_BASE (0xdeadbeef)
216 #define BCM_3368_PERF_BASE (0xfff8c000)
217 #define BCM_3368_TIMER_BASE (0xfff8c040)
218 #define BCM_3368_WDT_BASE (0xfff8c080)
219 #define BCM_3368_UART0_BASE (0xfff8c100)
220 #define BCM_3368_UART1_BASE (0xfff8c120)
221 #define BCM_3368_GPIO_BASE (0xfff8c080)
222 #define BCM_3368_SPI_BASE (0xfff8c800)
223 #define BCM_3368_HSSPI_BASE (0xdeadbeef)
224 #define BCM_3368_UDC0_BASE (0xdeadbeef)
225 #define BCM_3368_USBDMA_BASE (0xdeadbeef)
226 #define BCM_3368_OHCI0_BASE (0xdeadbeef)
227 #define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef)
228 #define BCM_3368_USBH_PRIV_BASE (0xdeadbeef)
229 #define BCM_3368_USBD_BASE (0xdeadbeef)
230 #define BCM_3368_MPI_BASE (0xfff80000)
231 #define BCM_3368_PCMCIA_BASE (0xfff80054)
232 #define BCM_3368_PCIE_BASE (0xdeadbeef)
233 #define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef)
234 #define BCM_3368_DSL_BASE (0xdeadbeef)
235 #define BCM_3368_UBUS_BASE (0xdeadbeef)
236 #define BCM_3368_ENET0_BASE (0xfff98000)
237 #define BCM_3368_ENET1_BASE (0xfff98800)
238 #define BCM_3368_ENETDMA_BASE (0xfff99800)
239 #define BCM_3368_ENETDMAC_BASE (0xfff99900)
240 #define BCM_3368_ENETDMAS_BASE (0xfff99a00)
241 #define BCM_3368_ENETSW_BASE (0xdeadbeef)
242 #define BCM_3368_EHCI0_BASE (0xdeadbeef)
243 #define BCM_3368_SDRAM_BASE (0xdeadbeef)
244 #define BCM_3368_MEMC_BASE (0xfff84000)
245 #define BCM_3368_DDR_BASE (0xdeadbeef)
246 #define BCM_3368_M2M_BASE (0xdeadbeef)
247 #define BCM_3368_ATM_BASE (0xdeadbeef)
248 #define BCM_3368_XTM_BASE (0xdeadbeef)
249 #define BCM_3368_XTMDMA_BASE (0xdeadbeef)
250 #define BCM_3368_XTMDMAC_BASE (0xdeadbeef)
251 #define BCM_3368_XTMDMAS_BASE (0xdeadbeef)
252 #define BCM_3368_PCM_BASE (0xfff9c200)
253 #define BCM_3368_PCMDMA_BASE (0xdeadbeef)
254 #define BCM_3368_PCMDMAC_BASE (0xdeadbeef)
255 #define BCM_3368_PCMDMAS_BASE (0xdeadbeef)
256 #define BCM_3368_RNG_BASE (0xdeadbeef)
257 #define BCM_3368_MISC_BASE (0xdeadbeef)
258
259 /*
199 260 * 6328 register sets base address
200 261 */
201 262 #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
… … static inline unsigned long bcm63xx_regs
633 694 #ifdef BCMCPU_RUNTIME_DETECT
634 695 return bcm63xx_regs_base[set];
635 696 #else
697 #ifdef CONFIG_BCM63XX_CPU_3368
698 __GEN_RSET(3368)
699 #endif
636 700 #ifdef CONFIG_BCM63XX_CPU_6328
637 701 __GEN_RSET(6328)
638 702 #endif
… … enum bcm63xx_irq {
701 765 };
702 766
703 767 /*
768 * 3368 irqs
769 */
770 #define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
771 #define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
772 #define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
773 #define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
774 #define BCM_3368_DSL_IRQ 0
775 #define BCM_3368_UDC0_IRQ 0
776 #define BCM_3368_OHCI0_IRQ 0
777 #define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
778 #define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
779 #define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
780 #define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
781 #define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
782 #define BCM_3368_HSSPI_IRQ 0
783 #define BCM_3368_EHCI0_IRQ 0
784 #define BCM_3368_USBD_IRQ 0
785 #define BCM_3368_USBD_RXDMA0_IRQ 0
786 #define BCM_3368_USBD_TXDMA0_IRQ 0
787 #define BCM_3368_USBD_RXDMA1_IRQ 0
788 #define BCM_3368_USBD_TXDMA1_IRQ 0
789 #define BCM_3368_USBD_RXDMA2_IRQ 0
790 #define BCM_3368_USBD_TXDMA2_IRQ 0
791 #define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
792 #define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
793 #define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
794 #define BCM_3368_PCMCIA_IRQ 0
795 #define BCM_3368_ATM_IRQ 0
796 #define BCM_3368_ENETSW_RXDMA0_IRQ 0
797 #define BCM_3368_ENETSW_RXDMA1_IRQ 0
798 #define BCM_3368_ENETSW_RXDMA2_IRQ 0
799 #define BCM_3368_ENETSW_RXDMA3_IRQ 0
800 #define BCM_3368_ENETSW_TXDMA0_IRQ 0
801 #define BCM_3368_ENETSW_TXDMA1_IRQ 0
802 #define BCM_3368_ENETSW_TXDMA2_IRQ 0
803 #define BCM_3368_ENETSW_TXDMA3_IRQ 0
804 #define BCM_3368_XTM_IRQ 0
805 #define BCM_3368_XTM_DMA0_IRQ 0
806
807 #define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
808 #define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
809 #define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
810 #define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
811
812
813 /*
704 814 * 6328 irqs
705 815 */
706 816 #define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
表式标准arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
a b static inline unsigned long bcm63xx_gpio
11 11 switch (bcm63xx_get_cpu_id()) {
12 12 case BCM6328_CPU_ID:
13 13 return 32;
14 case BCM3368_CPU_ID:
14 15 case BCM6358_CPU_ID:
15 16 return 40;
16 17 case BCM6338_CPU_ID:
表式标准arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
a b
15 15 /* Clock Control register */
16 16 #define PERF_CKCTL_REG 0x4
17 17
18 #define CKCTL_3368_MAC_EN (1 << 3)
19 #define CKCTL_3368_TC_EN (1 << 5)
20 #define CKCTL_3368_US_TOP_EN (1 << 6)
21 #define CKCTL_3368_DS_TOP_EN (1 << 7)
22 #define CKCTL_3368_APM_EN (1 << 8)
23 #define CKCTL_3368_SPI_EN (1 << 9)
24 #define CKCTL_3368_USBS_EN (1 << 10)
25 #define CKCTL_3368_BMU_EN (1 << 11)
26 #define CKCTL_3368_PCM_EN (1 << 12)
27 #define CKCTL_3368_NTP_EN (1 << 13)
28 #define CKCTL_3368_ACP_B_EN (1 << 14)
29 #define CKCTL_3368_ACP_A_EN (1 << 15)
30 #define CKCTL_3368_EMUSB_EN (1 << 17)
31 #define CKCTL_3368_ENET0_EN (1 << 18)
32 #define CKCTL_3368_ENET1_EN (1 << 19)
33 #define CKCTL_3368_USBU_EN (1 << 20)
34 #define CKCTL_3368_EPHY_EN (1 << 21)
35
36 #define CKCTL_3368_ALL_SAFE_EN (CKCTL_3368_MAC_EN | \
37 CKCTL_3368_TC_EN | \
38 CKCTL_3368_US_TOP_EN | \
39 CKCTL_3368_DS_TOP_EN | \
40 CKCTL_3368_APM_EN | \
41 CKCTL_3368_SPI_EN | \
42 CKCTL_3368_USBS_EN | \
43 CKCTL_3368_BMU_EN | \
44 CKCTL_3368_PCM_EN | \
45 CKCTL_3368_NTP_EN | \
46 CKCTL_3368_ACP_B_EN | \
47 CKCTL_3368_ACP_A_EN | \
48 CKCTL_3368_EMUSB_EN | \
49 CKCTL_3368_USBU_EN)
50
18 51 #define CKCTL_6328_PHYMIPS_EN (1 << 0)
19 52 #define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
20 53 #define CKCTL_6328_ADSL_AFE_EN (1 << 2)
… …
181 214 #define SYS_PLL_SOFT_RESET 0x1
182 215
183 216 /* Interrupt Mask register */
217 #define PERF_IRQMASK_3368_REG 0xc
184 218 #define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
185 219 #define PERF_IRQMASK_6338_REG 0xc
186 220 #define PERF_IRQMASK_6345_REG 0xc
… …
190 224 #define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
191 225
192 226 /* Interrupt Status register */
227 #define PERF_IRQSTAT_3368_REG 0x10
193 228 #define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
194 229 #define PERF_IRQSTAT_6338_REG 0x10
195 230 #define PERF_IRQSTAT_6345_REG 0x10
… …
199 234 #define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
200 235
201 236 /* External Interrupt Configuration register */
237 #define PERF_EXTIRQ_CFG_REG_3368 0x14
202 238 #define PERF_EXTIRQ_CFG_REG_6328 0x18
203 239 #define PERF_EXTIRQ_CFG_REG_6338 0x14
204 240 #define PERF_EXTIRQ_CFG_REG_6345 0x14
… …
1386 1422 #define SPI_6348_RX_DATA 0x80
1387 1423 #define SPI_6348_RX_DATA_SIZE 0x3f
1388 1424
1389 /* BCM 6358/6262/6368 SPI core */
1425 /* BCM 3368/6358/6262/6368 SPI core */
1390 1426 #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
1391 1427 #define SPI_6358_MSG_CTL_WIDTH 16
1392 1428 #define SPI_6358_MSG_DATA 0x02
表式标准arch/mips/include/asm/mach-bcm63xx/ioremap.h
a b static inline phys_t fixup_bigphys_addr(
11 11 static inline int is_bcm63xx_internal_registers(phys_t offset)
12 12 {
13 13 switch (bcm63xx_get_cpu_id()) {
14 case BCM3368_CPU_ID:
15 if (offset >= 0xfff80000)
16 return 1;
17 break;
14 18 case BCM6338_CPU_ID:
15 19 case BCM6345_CPU_ID:
16 20 case BCM6348_CPU_ID:
表式标准arch/mips/bcm63xx/irq.c
a b static DEFINE_SPINLOCK(ipic_lock);
33 33 static DEFINE_SPINLOCK(epic_lock);
34 34
35 35 #ifndef BCMCPU_RUNTIME_DETECT
36 #ifdef CONFIG_BCM63XX_CPU_3368
37 #define irq_stat_reg0 PERF_IRQSTAT_3368_REG
38 #define irq_mask_reg0 PERF_IRQMASK_3368_REG
39 #define irq_stat_reg1 0
40 #define irq_mask_reg1 0
41 #define irq_bits 32
42 #define is_ext_irq_cascaded 0
43 #define ext_irq_start 0
44 #define ext_irq_end 0
45 #define ext_irq_count 4
46 #define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_3368
47 #define ext_irq_cfg_reg2 0
48 #endif
36 49 #ifdef CONFIG_BCM63XX_CPU_6328
37 50 #define irq_stat_reg0 PERF_IRQSTAT_6328_REG(0)
38 51 #define irq_mask_reg0 PERF_IRQMASK_6328_REG(0)
… … static void bcm63xx_init_irq(void)
165 178 irq_mask_addr1 = bcm63xx_regset_address(RSET_PERF);
166 179
167 180 switch (bcm63xx_get_cpu_id()) {
181 case BCM3368_CPU_ID:
182 irq_stat_addr0 += PERF_IRQSTAT_3368_REG;
183 irq_mask_addr0 += PERF_IRQMASK_3368_REG;
184 irq_bits = 32;
185 ext_irq_count = 4;
186 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
187 break;
168 188 case BCM6328_CPU_ID:
169 189 irq_stat_addr0 += PERF_IRQSTAT_6328_REG(0);
170 190 irq_mask_addr0 += PERF_IRQMASK_6328_REG(0);
表式标准arch/mips/bcm63xx/dev-spi.c
a b static __init void bcm63xx_spi_regs_init
37 37 {
38 38 if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
39 39 bcm63xx_regs_spi = bcm6348_regs_spi;
40 if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
40 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
41 41 bcm63xx_regs_spi = bcm6358_regs_spi;
42 42 }
43 43 #else
… … int __init bcm63xx_spi_register(void)
87 87 spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;
88 88 }
89 89
90 if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
90 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||
91 BCMCPU_IS_6368()) {
91 92 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
92 93 spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
93 94 spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
表式标准arch/mips/bcm63xx/clk.c
a b static void enetx_set(struct clk *clk, i
84 84 else
85 85 clk_disable_unlocked(&clk_enet_misc);
86 86
87 if (BCMCPU_IS_6358()) {
87 if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
88 88 u32 mask;
89 89
90 90 if (clk->id == 0)
… … static struct clk clk_enet1 = {
110 110 */
111 111 static void ephy_set(struct clk *clk, int enable)
112 112 {
113 if (!BCMCPU_IS_6358())
114 return;
115 bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
113 if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
114 bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
116 115 }
117 116
118 117
… … static struct clk clk_enetsw = {
155 154 */
156 155 static void pcm_set(struct clk *clk, int enable)
157 156 {
158 if (!BCMCPU_IS_6358())
159 return;
160 bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
157 if (BCMCPU_IS_3368())
158 bcm_hwclock_set(CKCTL_3368_PCM_EN, enable);
159 if (BCMCPU_IS_6358())
160 bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
161 161 }
162 162
163 163 static struct clk clk_pcm = {
… … static void spi_set(struct clk *clk, int
221 221 mask = CKCTL_6338_SPI_EN;
222 222 else if (BCMCPU_IS_6348())
223 223 mask = CKCTL_6348_SPI_EN;
224 else if (BCMCPU_IS_6358())
224 else if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
225 225 mask = CKCTL_6358_SPI_EN;
226 226 else if (BCMCPU_IS_6362())
227 227 mask = CKCTL_6362_SPI_EN;
… … struct clk *clk_get(struct device *dev,
370 370 return &clk_xtm;
371 371 if (!strcmp(id, "periph"))
372 372 return &clk_periph;
373 if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
373 if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
374 374 return &clk_pcm;
375 375 if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
376 376 return &clk_ipsec;
表式标准arch/mips/bcm63xx/dev-flash.c
a b static int __init bcm63xx_detect_flash_t
102 102 /* no way to auto detect so assume parallel */
103 103 bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_PARALLEL;
104 104 break;
105 case BCM3368_CPU_ID:
105 106 case BCM6358_CPU_ID:
106 107 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
107 108 if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)
表式标准arch/mips/pci/pci-bcm63xx.c
a b static int __init bcm63xx_register_pci(v
266 266 /* setup PCI to local bus access, used by PCI device to target
267 267 * local RAM while bus mastering */
268 268 bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
269 if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
269 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368())
270 270 val = MPI_SP0_REMAP_ENABLE_MASK;
271 271 else
272 272 val = 0;
… … static int __init bcm63xx_pci_init(void)
338 338 case BCM6328_CPU_ID:
339 339 case BCM6362_CPU_ID:
340 340 return bcm63xx_register_pcie();
341 case BCM3368_CPU_ID:
341 342 case BCM6348_CPU_ID:
342 343 case BCM6358_CPU_ID:
343 344 case BCM6368_CPU_ID:
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คนไทย
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发表于 2013-11-3 23:53
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哪里写着支持modem了？
同是一小白的我，优哉游哉的路过。。。。
